The invention is related to the field of semiconductor fabrication, and in particular to fabricating highly tensile-strained Ge through lattice-mismatched heteroepitaxy on III-V templates.
In the last decade, strained-Si technology has been utilized to enhance the performance of metal-oxide-semiconductor field effect transistors (MOSFETs). To further improve the MOSFET performance, researchers have moved on to new materials with higher intrinsic carrier mobilities. Among these materials, Ge has been actively studied due to its intrinsically high hole mobility. To date, most of the MOSFETs utilizing Ge channels have been built on bulk Ge substrates or from compressively strained Ge thin films epitaxially grown on SiGe virtual substrates. Compressive strain enhances Ge hole mobility but degrades electron mobility, making it suitable for p-MOSFETs but disadvantageous for n-MOSFETs. It has been demonstrated that compressively strained Ge channels exhibit 10-12× hole mobility enhancement over Si channels. On the other hand, tensile-strained Ge has not been very well studied due to the difficulty of strain engineering with tensile Ge thin films. In theory, tensile strain enhances both electron and hole mobilities of Ge to levels much greater than those in unstrained or compressively-strained Ge and Si making it a highly promising channel material for future CMOS applications.